Systematical Evasion From Learning-Based Microarchitectural Attack Detection Tools
Published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (IEEE JETCAS), 2024
Because hardware vulnerabilities often cannot be patched quickly, machine learning-based detectors that monitor hardware performance counters at runtime have been proposed to catch microarchitectural attacks as they execute. This paper examines how robust those detectors really are. We build a fuzzing framework, composed of separate fuzzing blocks, that changes hardware performance counter values in a controlled way, and use it to modify attack source code so that it evades detection. The framework is evaluated in terms of time overhead, achieved leakage rate, and the number of trials needed to evade the detectors.
Recommended citation: D. R. Dipta, J. Tan and B. Gulmezoglu, "Systematical Evasion From Learning-Based Microarchitectural Attack Detection Tools," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (IEEE JETCAS), vol. 14, no. 4, pp. 823-833, Dec. 2024.
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