Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field
Published in 2019 International Conference on Electrical, Computer and Communication Engineering (ECCE), 2019
This paper presents an efficient hardware implementation of a 256-bit elliptic curve cryptography (ECC) processor over a prime field. The design targets FPGA platforms and optimizes both area and throughput through algorithmic and architectural co-design. The implementation supports standard cryptographic operations including point multiplication, which is the core operation for ECC-based protocols such as ECDH and ECDSA.
Recommended citation: M. S. Rahman, M. S. Hossain, E. H. Rahat, D. R. Dipta, H. M. R. Faruque and F. K. Fattah, "Efficient Hardware Implementation of 256-bit ECC Processor Over Prime Field," 2019 International Conference on Electrical, Computer and Communication Engineering (ECCE), Bangladesh, 2019.